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Macros</h2></td></tr>
<tr class="memitem:ga2742ac56c471a4ac8c605979d3bb0665"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga2742ac56c471a4ac8c605979d3bb0665">XUARTPSV_HW_H</a></td></tr>
<tr class="memdesc:ga2742ac56c471a4ac8c605979d3bb0665"><td class="mdescLeft">&#160;</td><td class="mdescRight">by using protection macros  <a href="group__uartpsv.html#ga2742ac56c471a4ac8c605979d3bb0665">More...</a><br/></td></tr>
<tr class="separator:ga2742ac56c471a4ac8c605979d3bb0665"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6272b3263e840a8218fc070c1656b9b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6272b3263e840a8218fc070c1656b9b9">XUartPsv_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:ga6272b3263e840a8218fc070c1656b9b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a UART register.  <a href="group__uartpsv.html#ga6272b3263e840a8218fc070c1656b9b9">More...</a><br/></td></tr>
<tr class="separator:ga6272b3263e840a8218fc070c1656b9b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fcbc3ad3fd4949b016ae362929ee344"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1fcbc3ad3fd4949b016ae362929ee344">XUartPsv_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)</td></tr>
<tr class="memdesc:ga1fcbc3ad3fd4949b016ae362929ee344"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a UART register.  <a href="group__uartpsv.html#ga1fcbc3ad3fd4949b016ae362929ee344">More...</a><br/></td></tr>
<tr class="separator:ga1fcbc3ad3fd4949b016ae362929ee344"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72e127b91f03728e0b58b2b3b6373dd9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga72e127b91f03728e0b58b2b3b6373dd9">XUartPsv_IsReceiveData</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga72e127b91f03728e0b58b2b3b6373dd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if there is receive data in the receiver and/or FIFO.  <a href="group__uartpsv.html#ga72e127b91f03728e0b58b2b3b6373dd9">More...</a><br/></td></tr>
<tr class="separator:ga72e127b91f03728e0b58b2b3b6373dd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04b62e0a1ad868d0a75238356c973336"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga04b62e0a1ad868d0a75238356c973336">XUartPsv_IsTransmitFull</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga04b62e0a1ad868d0a75238356c973336"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a byte of data can be sent with the transmitter.  <a href="group__uartpsv.html#ga04b62e0a1ad868d0a75238356c973336">More...</a><br/></td></tr>
<tr class="separator:ga04b62e0a1ad868d0a75238356c973336"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ff4c2f51e7f3e9a5d0b017c841a7ab3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9ff4c2f51e7f3e9a5d0b017c841a7ab3">XUartPsv_IsTransmitbusy</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga9ff4c2f51e7f3e9a5d0b017c841a7ab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a byte of data can be sent with the transmitter.  <a href="group__uartpsv.html#ga9ff4c2f51e7f3e9a5d0b017c841a7ab3">More...</a><br/></td></tr>
<tr class="separator:ga9ff4c2f51e7f3e9a5d0b017c841a7ab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the UART. </p>
</div></td></tr>
<tr class="memitem:ga101fd40e38eabc4ac374e9f332a71b46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga101fd40e38eabc4ac374e9f332a71b46">XUARTPSV_UARTDR_OFFSET</a>&#160;&#160;&#160;0x0000U</td></tr>
<tr class="memdesc:ga101fd40e38eabc4ac374e9f332a71b46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data.  <a href="group__uartpsv.html#ga101fd40e38eabc4ac374e9f332a71b46">More...</a><br/></td></tr>
<tr class="separator:ga101fd40e38eabc4ac374e9f332a71b46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65163bef9c7aeef0a20ecd553ab0812a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga65163bef9c7aeef0a20ecd553ab0812a">XUARTPSV_UARTRSR_OFFSET</a>&#160;&#160;&#160;0x0004U</td></tr>
<tr class="memdesc:ga65163bef9c7aeef0a20ecd553ab0812a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Status Register/Error Clear.  <a href="group__uartpsv.html#ga65163bef9c7aeef0a20ecd553ab0812a">More...</a><br/></td></tr>
<tr class="separator:ga65163bef9c7aeef0a20ecd553ab0812a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f04dd68cd110b79baf2076b0564eadd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3f04dd68cd110b79baf2076b0564eadd">XUARTPSV_UARTFR_OFFSET</a>&#160;&#160;&#160;0x0018U</td></tr>
<tr class="memdesc:ga3f04dd68cd110b79baf2076b0564eadd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flag Register.  <a href="group__uartpsv.html#ga3f04dd68cd110b79baf2076b0564eadd">More...</a><br/></td></tr>
<tr class="separator:ga3f04dd68cd110b79baf2076b0564eadd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga258ffb7e79eeabd1ec1273b4f9998071"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga258ffb7e79eeabd1ec1273b4f9998071">XUARTPSV_UARTILPR_OFFSET</a>&#160;&#160;&#160;0x0020U</td></tr>
<tr class="memdesc:ga258ffb7e79eeabd1ec1273b4f9998071"><td class="mdescLeft">&#160;</td><td class="mdescRight">IrDA Low-Power Counter.  <a href="group__uartpsv.html#ga258ffb7e79eeabd1ec1273b4f9998071">More...</a><br/></td></tr>
<tr class="separator:ga258ffb7e79eeabd1ec1273b4f9998071"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga773416a8d139d13f464660701a96b091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga773416a8d139d13f464660701a96b091">XUARTPSV_UARTIBRD_OFFSET</a>&#160;&#160;&#160;0x0024U</td></tr>
<tr class="memdesc:ga773416a8d139d13f464660701a96b091"><td class="mdescLeft">&#160;</td><td class="mdescRight">Integer Baud Rate.  <a href="group__uartpsv.html#ga773416a8d139d13f464660701a96b091">More...</a><br/></td></tr>
<tr class="separator:ga773416a8d139d13f464660701a96b091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5cbf5b3dfdfd11d7e9f62d1fabba3cd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga5cbf5b3dfdfd11d7e9f62d1fabba3cd7">XUARTPSV_UARTFBRD_OFFSET</a>&#160;&#160;&#160;0x0028U</td></tr>
<tr class="memdesc:ga5cbf5b3dfdfd11d7e9f62d1fabba3cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fractional Baud Rate.  <a href="group__uartpsv.html#ga5cbf5b3dfdfd11d7e9f62d1fabba3cd7">More...</a><br/></td></tr>
<tr class="separator:ga5cbf5b3dfdfd11d7e9f62d1fabba3cd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08c3dd57fdf59ae1e0cf866476e81c38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga08c3dd57fdf59ae1e0cf866476e81c38">XUARTPSV_UARTLCR_OFFSET</a>&#160;&#160;&#160;0x002CU</td></tr>
<tr class="memdesc:ga08c3dd57fdf59ae1e0cf866476e81c38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Control.  <a href="group__uartpsv.html#ga08c3dd57fdf59ae1e0cf866476e81c38">More...</a><br/></td></tr>
<tr class="separator:ga08c3dd57fdf59ae1e0cf866476e81c38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga107036ece577d1e34edf6c01eb83305e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga107036ece577d1e34edf6c01eb83305e">XUARTPSV_UARTCR_OFFSET</a>&#160;&#160;&#160;0x0030U</td></tr>
<tr class="memdesc:ga107036ece577d1e34edf6c01eb83305e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control.  <a href="group__uartpsv.html#ga107036ece577d1e34edf6c01eb83305e">More...</a><br/></td></tr>
<tr class="separator:ga107036ece577d1e34edf6c01eb83305e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd10d435731ec271f5316110cde0c6e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gacd10d435731ec271f5316110cde0c6e9">XUARTPSV_UARTIFLS_OFFSET</a>&#160;&#160;&#160;0x0034U</td></tr>
<tr class="memdesc:gacd10d435731ec271f5316110cde0c6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt FIFO Level Select.  <a href="group__uartpsv.html#gacd10d435731ec271f5316110cde0c6e9">More...</a><br/></td></tr>
<tr class="separator:gacd10d435731ec271f5316110cde0c6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cb9a381f2ea7582c0f361fbe2a77246"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga0cb9a381f2ea7582c0f361fbe2a77246">XUARTPSV_UARTIMSC_OFFSET</a>&#160;&#160;&#160;0x0038U</td></tr>
<tr class="memdesc:ga0cb9a381f2ea7582c0f361fbe2a77246"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Set/Clear.  <a href="group__uartpsv.html#ga0cb9a381f2ea7582c0f361fbe2a77246">More...</a><br/></td></tr>
<tr class="separator:ga0cb9a381f2ea7582c0f361fbe2a77246"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae409fde818bb1e9093340a7713c416ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gae409fde818bb1e9093340a7713c416ee">XUARTPSV_UARTRIS_OFFSET</a>&#160;&#160;&#160;0x003CU</td></tr>
<tr class="memdesc:gae409fde818bb1e9093340a7713c416ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Raw interrupt Status.  <a href="group__uartpsv.html#gae409fde818bb1e9093340a7713c416ee">More...</a><br/></td></tr>
<tr class="separator:gae409fde818bb1e9093340a7713c416ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf39dadddb814aecf4fbfa95e9635b767"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaf39dadddb814aecf4fbfa95e9635b767">XUARTPSV_UARTMIS_OFFSET</a>&#160;&#160;&#160;0x0040U</td></tr>
<tr class="memdesc:gaf39dadddb814aecf4fbfa95e9635b767"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask interrupt Status.  <a href="group__uartpsv.html#gaf39dadddb814aecf4fbfa95e9635b767">More...</a><br/></td></tr>
<tr class="separator:gaf39dadddb814aecf4fbfa95e9635b767"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57aee99ed20e8b0a6c2529abe80d8a62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga57aee99ed20e8b0a6c2529abe80d8a62">XUARTPSV_UARTICR_OFFSET</a>&#160;&#160;&#160;0x0044U</td></tr>
<tr class="memdesc:ga57aee99ed20e8b0a6c2529abe80d8a62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Clear.  <a href="group__uartpsv.html#ga57aee99ed20e8b0a6c2529abe80d8a62">More...</a><br/></td></tr>
<tr class="separator:ga57aee99ed20e8b0a6c2529abe80d8a62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40371d744cb94a43e538a7e13c93dc36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga40371d744cb94a43e538a7e13c93dc36">XUARTPSV_UARTDMACR_OFFSET</a>&#160;&#160;&#160;0x0048U</td></tr>
<tr class="memdesc:ga40371d744cb94a43e538a7e13c93dc36"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Control.  <a href="group__uartpsv.html#ga40371d744cb94a43e538a7e13c93dc36">More...</a><br/></td></tr>
<tr class="separator:ga40371d744cb94a43e538a7e13c93dc36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receive status register/error clear register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Receive status register/error clear register (UARTRSR) gives the status of break, frame, parity and overrun.</p>
<p>Receive status register/error clear register Bit Definition </p>
</div></td></tr>
<tr class="memitem:gaef8dbb9828f6d363739c9093af53e234"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaef8dbb9828f6d363739c9093af53e234">XUARTPSV_UARTRSR_OE</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaef8dbb9828f6d363739c9093af53e234"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overrun error.  <a href="group__uartpsv.html#gaef8dbb9828f6d363739c9093af53e234">More...</a><br/></td></tr>
<tr class="separator:gaef8dbb9828f6d363739c9093af53e234"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Flag Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Flag register (UARTFR)</p>
<p>Flag Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:gab3a0cfba6e8eae498e57ab69a462039b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab3a0cfba6e8eae498e57ab69a462039b">XUARTPSV_UARTFR_RI</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:gab3a0cfba6e8eae498e57ab69a462039b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ring indicator.  <a href="group__uartpsv.html#gab3a0cfba6e8eae498e57ab69a462039b">More...</a><br/></td></tr>
<tr class="separator:gab3a0cfba6e8eae498e57ab69a462039b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac52469fbe1e3bb8ce53bf2c61833389d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac52469fbe1e3bb8ce53bf2c61833389d">XUARTPSV_UARTFR_TXFE</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gac52469fbe1e3bb8ce53bf2c61833389d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO empty.  <a href="group__uartpsv.html#gac52469fbe1e3bb8ce53bf2c61833389d">More...</a><br/></td></tr>
<tr class="separator:gac52469fbe1e3bb8ce53bf2c61833389d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bb5361dcedf7b4a04f91ec8b5b66feb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6bb5361dcedf7b4a04f91ec8b5b66feb">XUARTPSV_UARTFR_RXFF</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga6bb5361dcedf7b4a04f91ec8b5b66feb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO full.  <a href="group__uartpsv.html#ga6bb5361dcedf7b4a04f91ec8b5b66feb">More...</a><br/></td></tr>
<tr class="separator:ga6bb5361dcedf7b4a04f91ec8b5b66feb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41a86bcc1a37151cff70ef6d9c8779c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga41a86bcc1a37151cff70ef6d9c8779c1">XUARTPSV_UARTFR_TXFF</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga41a86bcc1a37151cff70ef6d9c8779c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO full.  <a href="group__uartpsv.html#ga41a86bcc1a37151cff70ef6d9c8779c1">More...</a><br/></td></tr>
<tr class="separator:ga41a86bcc1a37151cff70ef6d9c8779c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52d6f333914d8bde4a32dff6022edcf7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga52d6f333914d8bde4a32dff6022edcf7">XUARTPSV_UARTFR_RXFE</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga52d6f333914d8bde4a32dff6022edcf7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO empty.  <a href="group__uartpsv.html#ga52d6f333914d8bde4a32dff6022edcf7">More...</a><br/></td></tr>
<tr class="separator:ga52d6f333914d8bde4a32dff6022edcf7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ad13f5d5d544fb2ba1df04f5b02d2b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9ad13f5d5d544fb2ba1df04f5b02d2b5">XUARTPSV_UARTFR_BUSY</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9ad13f5d5d544fb2ba1df04f5b02d2b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Busy.  <a href="group__uartpsv.html#ga9ad13f5d5d544fb2ba1df04f5b02d2b5">More...</a><br/></td></tr>
<tr class="separator:ga9ad13f5d5d544fb2ba1df04f5b02d2b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba19046e28a269709df4f068f9f170cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaba19046e28a269709df4f068f9f170cb">XUARTPSV_UARTFR_DCD</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gaba19046e28a269709df4f068f9f170cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data carrier detect.  <a href="group__uartpsv.html#gaba19046e28a269709df4f068f9f170cb">More...</a><br/></td></tr>
<tr class="separator:gaba19046e28a269709df4f068f9f170cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ec770093d281d7cbeadeec852510ac2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9ec770093d281d7cbeadeec852510ac2">XUARTPSV_UARTFR_DSR</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga9ec770093d281d7cbeadeec852510ac2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data set ready.  <a href="group__uartpsv.html#ga9ec770093d281d7cbeadeec852510ac2">More...</a><br/></td></tr>
<tr class="separator:ga9ec770093d281d7cbeadeec852510ac2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd47c932f4af87234dbf9eae54d36ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gacd47c932f4af87234dbf9eae54d36ee2">XUARTPSV_UARTFR_CTS</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gacd47c932f4af87234dbf9eae54d36ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear to send.  <a href="group__uartpsv.html#gacd47c932f4af87234dbf9eae54d36ee2">More...</a><br/></td></tr>
<tr class="separator:gacd47c932f4af87234dbf9eae54d36ee2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Line Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Line Control register (UARTLCR) controls the functions of the device.</p>
<p>Line Control Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga4f9741a2e041289f4d8ed30131801532"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga4f9741a2e041289f4d8ed30131801532">XUARTPSV_UARTLCR_SPS</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga4f9741a2e041289f4d8ed30131801532"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stick parity select.  <a href="group__uartpsv.html#ga4f9741a2e041289f4d8ed30131801532">More...</a><br/></td></tr>
<tr class="separator:ga4f9741a2e041289f4d8ed30131801532"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga452535571ef19b6c387d2823040ba3da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga452535571ef19b6c387d2823040ba3da">XUARTPSV_UARTLCR_FEN</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga452535571ef19b6c387d2823040ba3da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable FIFOs.  <a href="group__uartpsv.html#ga452535571ef19b6c387d2823040ba3da">More...</a><br/></td></tr>
<tr class="separator:ga452535571ef19b6c387d2823040ba3da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3be3c6c5c218776ac18f288c5436f6d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3be3c6c5c218776ac18f288c5436f6d3">XUARTPSV_UARTLCR_STP2</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga3be3c6c5c218776ac18f288c5436f6d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Two stop bits selected.  <a href="group__uartpsv.html#ga3be3c6c5c218776ac18f288c5436f6d3">More...</a><br/></td></tr>
<tr class="separator:ga3be3c6c5c218776ac18f288c5436f6d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae3f5b99936ef4eb655ce2ab16d377e11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gae3f5b99936ef4eb655ce2ab16d377e11">XUARTPSV_UARTLCR_EPS</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gae3f5b99936ef4eb655ce2ab16d377e11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Even parity select.  <a href="group__uartpsv.html#gae3f5b99936ef4eb655ce2ab16d377e11">More...</a><br/></td></tr>
<tr class="separator:gae3f5b99936ef4eb655ce2ab16d377e11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7d53791827c54fb0170ebb9c5d8fa21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaa7d53791827c54fb0170ebb9c5d8fa21">XUARTPSV_UARTLCR_PEN</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa7d53791827c54fb0170ebb9c5d8fa21"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity enable.  <a href="group__uartpsv.html#gaa7d53791827c54fb0170ebb9c5d8fa21">More...</a><br/></td></tr>
<tr class="separator:gaa7d53791827c54fb0170ebb9c5d8fa21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a415054abfc09f2e9fc92c592feb074"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga7a415054abfc09f2e9fc92c592feb074">XUARTPSV_UARTLCR_BRK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga7a415054abfc09f2e9fc92c592feb074"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send break.  <a href="group__uartpsv.html#ga7a415054abfc09f2e9fc92c592feb074">More...</a><br/></td></tr>
<tr class="separator:ga7a415054abfc09f2e9fc92c592feb074"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1023547ed388849703da403fe34b2bcb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1023547ed388849703da403fe34b2bcb">XUARTPSV_UARTLCR_WLEN_MASK</a>&#160;&#160;&#160;0x00000060U</td></tr>
<tr class="memdesc:ga1023547ed388849703da403fe34b2bcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word length mask.  <a href="group__uartpsv.html#ga1023547ed388849703da403fe34b2bcb">More...</a><br/></td></tr>
<tr class="separator:ga1023547ed388849703da403fe34b2bcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafef090600c5845be229c5767c8fbfec2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gafef090600c5845be229c5767c8fbfec2">XUARTPSV_UARTLCR_WLEN_SHIFT</a>&#160;&#160;&#160;0x00000005U</td></tr>
<tr class="memdesc:gafef090600c5845be229c5767c8fbfec2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word length shift.  <a href="group__uartpsv.html#gafef090600c5845be229c5767c8fbfec2">More...</a><br/></td></tr>
<tr class="separator:gafef090600c5845be229c5767c8fbfec2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06e89aabb2efafac0395062a96d2b0c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga06e89aabb2efafac0395062a96d2b0c0">XUARTPSV_UARTLCR_WLEN_5_BIT</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga06e89aabb2efafac0395062a96d2b0c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">5 bits data  <a href="group__uartpsv.html#ga06e89aabb2efafac0395062a96d2b0c0">More...</a><br/></td></tr>
<tr class="separator:ga06e89aabb2efafac0395062a96d2b0c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7ecba2331efa67484848e2a0829e74a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac7ecba2331efa67484848e2a0829e74a">XUARTPSV_UARTLCR_WLEN_6_BIT</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gac7ecba2331efa67484848e2a0829e74a"><td class="mdescLeft">&#160;</td><td class="mdescRight">6 bits data  <a href="group__uartpsv.html#gac7ecba2331efa67484848e2a0829e74a">More...</a><br/></td></tr>
<tr class="separator:gac7ecba2331efa67484848e2a0829e74a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fd25f767bf9cfab442e6ec68a5befd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6fd25f767bf9cfab442e6ec68a5befd2">XUARTPSV_UARTLCR_WLEN_7_BIT</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga6fd25f767bf9cfab442e6ec68a5befd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">7 bits data  <a href="group__uartpsv.html#ga6fd25f767bf9cfab442e6ec68a5befd2">More...</a><br/></td></tr>
<tr class="separator:ga6fd25f767bf9cfab442e6ec68a5befd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga335f08fb476df8eb3efc3c6de1290048"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga335f08fb476df8eb3efc3c6de1290048">XUARTPSV_UARTLCR_WLEN_8_BIT</a>&#160;&#160;&#160;0x00000060U</td></tr>
<tr class="memdesc:ga335f08fb476df8eb3efc3c6de1290048"><td class="mdescLeft">&#160;</td><td class="mdescRight">8 bits data  <a href="group__uartpsv.html#ga335f08fb476df8eb3efc3c6de1290048">More...</a><br/></td></tr>
<tr class="separator:ga335f08fb476df8eb3efc3c6de1290048"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a1258712defca4ca15587be8803f6e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga0a1258712defca4ca15587be8803f6e7">XUARTPSV_UARTLCR_STP_1_BIT</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga0a1258712defca4ca15587be8803f6e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">One stop bits selected.  <a href="group__uartpsv.html#ga0a1258712defca4ca15587be8803f6e7">More...</a><br/></td></tr>
<tr class="separator:ga0a1258712defca4ca15587be8803f6e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a5c571c8766fc2ab6843a2c6e8bbca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga2a5c571c8766fc2ab6843a2c6e8bbca1">XUARTPSV_UARTLCR_STP_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga2a5c571c8766fc2ab6843a2c6e8bbca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop bits mask.  <a href="group__uartpsv.html#ga2a5c571c8766fc2ab6843a2c6e8bbca1">More...</a><br/></td></tr>
<tr class="separator:ga2a5c571c8766fc2ab6843a2c6e8bbca1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5ae863cb8547fdc9d63183cd44ae1ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac5ae863cb8547fdc9d63183cd44ae1ff">XUARTPSV_UARTLCR_STP_SHIFT</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gac5ae863cb8547fdc9d63183cd44ae1ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop bits shift.  <a href="group__uartpsv.html#gac5ae863cb8547fdc9d63183cd44ae1ff">More...</a><br/></td></tr>
<tr class="separator:gac5ae863cb8547fdc9d63183cd44ae1ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb9516848687daeb773f67f81c39267d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gacb9516848687daeb773f67f81c39267d">XUARTPSV_UARTLCR_PARITY_EVEN</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gacb9516848687daeb773f67f81c39267d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Even parity mode.  <a href="group__uartpsv.html#gacb9516848687daeb773f67f81c39267d">More...</a><br/></td></tr>
<tr class="separator:gacb9516848687daeb773f67f81c39267d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b94a4115ed1352d692b6c7edb1c328a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga0b94a4115ed1352d692b6c7edb1c328a">XUARTPSV_UARTLCR_PARITY_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga0b94a4115ed1352d692b6c7edb1c328a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity mask.  <a href="group__uartpsv.html#ga0b94a4115ed1352d692b6c7edb1c328a">More...</a><br/></td></tr>
<tr class="separator:ga0b94a4115ed1352d692b6c7edb1c328a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc334d01b7ef2ffd237cd0ebc0e24877"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gacc334d01b7ef2ffd237cd0ebc0e24877">XUARTPSV_UARTLCR_PARITY_SHIFT</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gacc334d01b7ef2ffd237cd0ebc0e24877"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity shift.  <a href="group__uartpsv.html#gacc334d01b7ef2ffd237cd0ebc0e24877">More...</a><br/></td></tr>
<tr class="separator:gacc334d01b7ef2ffd237cd0ebc0e24877"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35ad48f37d89982a7abb1b2e73f1726d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga35ad48f37d89982a7abb1b2e73f1726d">XUARTPSV_UARTLCR_PARITY_NONE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga35ad48f37d89982a7abb1b2e73f1726d"><td class="mdescLeft">&#160;</td><td class="mdescRight">No parity mode.  <a href="group__uartpsv.html#ga35ad48f37d89982a7abb1b2e73f1726d">More...</a><br/></td></tr>
<tr class="separator:ga35ad48f37d89982a7abb1b2e73f1726d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3191c3f1ae49b82681725f8655eb50c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3191c3f1ae49b82681725f8655eb50c1">XUARTPSV_UARTLCR_PARITY_ODD</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga3191c3f1ae49b82681725f8655eb50c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Odd parity mode.  <a href="group__uartpsv.html#ga3191c3f1ae49b82681725f8655eb50c1">More...</a><br/></td></tr>
<tr class="separator:ga3191c3f1ae49b82681725f8655eb50c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Control register (UARTCR) controls the major functions of the device.</p>
<p>Control Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga9aed4ef6f7b607ee998086b4ccd1470a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9aed4ef6f7b607ee998086b4ccd1470a">XUARTPSV_UARTCR_CTSEN</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga9aed4ef6f7b607ee998086b4ccd1470a"><td class="mdescLeft">&#160;</td><td class="mdescRight">CTS hardware flow control enable.  <a href="group__uartpsv.html#ga9aed4ef6f7b607ee998086b4ccd1470a">More...</a><br/></td></tr>
<tr class="separator:ga9aed4ef6f7b607ee998086b4ccd1470a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga370276d7952d37b3975e122f130e2966"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga370276d7952d37b3975e122f130e2966">XUARTPSV_UARTCR_RTSEN</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:ga370276d7952d37b3975e122f130e2966"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTS hardware flow control enable.  <a href="group__uartpsv.html#ga370276d7952d37b3975e122f130e2966">More...</a><br/></td></tr>
<tr class="separator:ga370276d7952d37b3975e122f130e2966"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd808993b004215aec5e78e26b228fea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gafd808993b004215aec5e78e26b228fea">XUARTPSV_UARTCR_OUT2</a>&#160;&#160;&#160;0x00002000U</td></tr>
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<tr class="memitem:ga885d95f43b5bcea2f29cd9bb280472fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga885d95f43b5bcea2f29cd9bb280472fc">XUARTPSV_UARTCR_RXE</a>&#160;&#160;&#160;0x00000200U</td></tr>
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<tr class="memitem:ga970380af9fdaa61e3bc1531645cc0f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga970380af9fdaa61e3bc1531645cc0f19">XUARTPSV_UARTCR_TXE</a>&#160;&#160;&#160;0x00000100U</td></tr>
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<tr class="memitem:gae2e178647eee834f64b7f478fdd23cfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gae2e178647eee834f64b7f478fdd23cfa">XUARTPSV_UARTCR_LBE</a>&#160;&#160;&#160;0x00000080U</td></tr>
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<tr class="memitem:ga7232cc7661b65d65b04d589279f4c94f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga7232cc7661b65d65b04d589279f4c94f">XUARTPSV_UARTCR_SIRLP</a>&#160;&#160;&#160;0x00000004U</td></tr>
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<tr class="memitem:ga9e8f865ef4d2e239cf655b698361199a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9e8f865ef4d2e239cf655b698361199a">XUARTPSV_UARTCR_SIREN</a>&#160;&#160;&#160;0x00000002U</td></tr>
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<tr class="memitem:gad2f1a7f666dec76a2673c6c7dbb2be2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gad2f1a7f666dec76a2673c6c7dbb2be2f">XUARTPSV_UARTCR_UARTEN</a>&#160;&#160;&#160;0x00000001U</td></tr>
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<tr class="memitem:ga1a0baa260d70d4282cdb57ed1b678e33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1a0baa260d70d4282cdb57ed1b678e33">XUARTPSV_UARTCR_MODE_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
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<tr class="memitem:ga3cb7344a223ea2c7dc3d4bc6be3d387d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3cb7344a223ea2c7dc3d4bc6be3d387d">XUARTPSV_UARTCR_MODE_SHIFT</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga3cb7344a223ea2c7dc3d4bc6be3d387d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode shift.  <a href="group__uartpsv.html#ga3cb7344a223ea2c7dc3d4bc6be3d387d">More...</a><br/></td></tr>
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<tr class="memitem:ga1fcf5d1f1e8b57514f6538f89ce7bfd5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1fcf5d1f1e8b57514f6538f89ce7bfd5">XUARTPSV_UARTCR_MODE_NORMAL</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga1fcf5d1f1e8b57514f6538f89ce7bfd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Normal Mode.  <a href="group__uartpsv.html#ga1fcf5d1f1e8b57514f6538f89ce7bfd5">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt FIFO Level Select Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTIFLS Register is the interrupt FIFO level select register.</p>
<p>You can use this register to define the FIFO level that triggers the assertion of UARTTXINTR and UARTRXINTR.</p>
<p>Interrupt FIFO Level Select Register Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga3149c045f35eae100cb9f39765796327"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3149c045f35eae100cb9f39765796327">XUARTPSV_UARTIFLS_RXIFLSEL_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga3149c045f35eae100cb9f39765796327"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive interrupt FIFO level select mask.  <a href="group__uartpsv.html#ga3149c045f35eae100cb9f39765796327">More...</a><br/></td></tr>
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<tr class="memitem:ga62086b945a7d3da80892a619abe3671b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga62086b945a7d3da80892a619abe3671b">XUARTPSV_UARTIFLS_RXIFLSEL_SHIFT</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga62086b945a7d3da80892a619abe3671b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit interrupt FIFO level select shift.  <a href="group__uartpsv.html#ga62086b945a7d3da80892a619abe3671b">More...</a><br/></td></tr>
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<tr class="memitem:ga1fc7d66bafa6dd862f0bbb2648721aa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1fc7d66bafa6dd862f0bbb2648721aa9">XUARTPSV_UARTIFLS_TXIFLSEL_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga1fc7d66bafa6dd862f0bbb2648721aa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive interrupt FIFO level select mask.  <a href="group__uartpsv.html#ga1fc7d66bafa6dd862f0bbb2648721aa9">More...</a><br/></td></tr>
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<tr class="memitem:ga30b5d2120c2571ea1102e12ff4d322b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga30b5d2120c2571ea1102e12ff4d322b1">XUARTPSV_UARTIFLS_TXIFLSEL_SHIFT</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga30b5d2120c2571ea1102e12ff4d322b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit interrupt FIFO level select shift.  <a href="group__uartpsv.html#ga30b5d2120c2571ea1102e12ff4d322b1">More...</a><br/></td></tr>
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<tr class="memitem:gac2f2edef72d9b490c98d2dd8a86986ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac2f2edef72d9b490c98d2dd8a86986ab">XUARTPSV_UARTIFLS_RXIFLSEL_1_8</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gac2f2edef72d9b490c98d2dd8a86986ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO becomes .  <a href="group__uartpsv.html#gac2f2edef72d9b490c98d2dd8a86986ab">More...</a><br/></td></tr>
<tr class="separator:gac2f2edef72d9b490c98d2dd8a86986ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdfa0dbb23e485a516ca374f17188afc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gafdfa0dbb23e485a516ca374f17188afc">XUARTPSV_UARTIFLS_RXIFLSEL_1_4</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gafdfa0dbb23e485a516ca374f17188afc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO becomes .  <a href="group__uartpsv.html#gafdfa0dbb23e485a516ca374f17188afc">More...</a><br/></td></tr>
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<tr class="memitem:gaa8188b89d0ce92a1f44a6567f36697a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaa8188b89d0ce92a1f44a6567f36697a0">XUARTPSV_UARTIFLS_RXIFLSEL_1_2</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gaa8188b89d0ce92a1f44a6567f36697a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO becomes * .  <a href="group__uartpsv.html#gaa8188b89d0ce92a1f44a6567f36697a0">More...</a><br/></td></tr>
<tr class="separator:gaa8188b89d0ce92a1f44a6567f36697a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47b47523cca78afa6e52a9502027a37c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga47b47523cca78afa6e52a9502027a37c">XUARTPSV_UARTIFLS_RXIFLSEL_3_4</a>&#160;&#160;&#160;0x00000018U</td></tr>
<tr class="memdesc:ga47b47523cca78afa6e52a9502027a37c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO becomes * .  <a href="group__uartpsv.html#ga47b47523cca78afa6e52a9502027a37c">More...</a><br/></td></tr>
<tr class="separator:ga47b47523cca78afa6e52a9502027a37c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c032ea161c7f4c3b0f324fbaac3f5c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga5c032ea161c7f4c3b0f324fbaac3f5c3">XUARTPSV_UARTIFLS_RXIFLSEL_7_8</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga5c032ea161c7f4c3b0f324fbaac3f5c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO becomes * .  <a href="group__uartpsv.html#ga5c032ea161c7f4c3b0f324fbaac3f5c3">More...</a><br/></td></tr>
<tr class="separator:ga5c032ea161c7f4c3b0f324fbaac3f5c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a1f2150559e66e8dc7dc3a6302e9f73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6a1f2150559e66e8dc7dc3a6302e9f73">XUARTPSV_UARTIFLS_TXIFLSEL_1_8</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga6a1f2150559e66e8dc7dc3a6302e9f73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO becomes * .  <a href="group__uartpsv.html#ga6a1f2150559e66e8dc7dc3a6302e9f73">More...</a><br/></td></tr>
<tr class="separator:ga6a1f2150559e66e8dc7dc3a6302e9f73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga531cc265bba0a0fa20238cccebfafc22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga531cc265bba0a0fa20238cccebfafc22">XUARTPSV_UARTIFLS_TXIFLSEL_1_4</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga531cc265bba0a0fa20238cccebfafc22"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO becomes * .  <a href="group__uartpsv.html#ga531cc265bba0a0fa20238cccebfafc22">More...</a><br/></td></tr>
<tr class="separator:ga531cc265bba0a0fa20238cccebfafc22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9dcd25c0d3978163c3f86f84bf9842ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9dcd25c0d3978163c3f86f84bf9842ee">XUARTPSV_UARTIFLS_TXIFLSEL_1_2</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga9dcd25c0d3978163c3f86f84bf9842ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO becomes * .  <a href="group__uartpsv.html#ga9dcd25c0d3978163c3f86f84bf9842ee">More...</a><br/></td></tr>
<tr class="separator:ga9dcd25c0d3978163c3f86f84bf9842ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac105b9cbc51795e15c03a933bef1aaae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac105b9cbc51795e15c03a933bef1aaae">XUARTPSV_UARTIFLS_TXIFLSEL_3_4</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:gac105b9cbc51795e15c03a933bef1aaae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO becomes * .  <a href="group__uartpsv.html#gac105b9cbc51795e15c03a933bef1aaae">More...</a><br/></td></tr>
<tr class="separator:gac105b9cbc51795e15c03a933bef1aaae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba65dd48c679c42014b22e3218f9ae03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaba65dd48c679c42014b22e3218f9ae03">XUARTPSV_UARTIFLS_TXIFLSEL_7_8</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gaba65dd48c679c42014b22e3218f9ae03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit FIFO becomes * .  <a href="group__uartpsv.html#gaba65dd48c679c42014b22e3218f9ae03">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Mask Set/Clear Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTIMSC Register is the interrupt mask set/clear register.</p>
<p>It is a read/write register. On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask.</p>
<p>Interrupt Mask Set/Clear Register Bit Definition </p>
</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Raw Interrupt Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The raw interrupt status register (UARTRIS) is a read-only register.</p>
<p>This register returns the current raw status value, prior to masking, of the corresponding interrupt. A write has no effect.</p>
<p>Raw Interrupt Status Register Bit Definition </p>
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<tr class="memitem:gad8e6dbbb885dc5746daeefd03576fd64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gad8e6dbbb885dc5746daeefd03576fd64">XUARTPSV_UARTRIS_OERIS</a>&#160;&#160;&#160;0x00000400U</td></tr>
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<tr class="memitem:ga17fbfe1af8b3e0afeebb101d38831356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga17fbfe1af8b3e0afeebb101d38831356">XUARTPSV_UARTRIS_RXRIS</a>&#160;&#160;&#160;0x00000010U</td></tr>
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<tr class="memitem:ga212984492952ed44c8cc5f1f2c21b88b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga212984492952ed44c8cc5f1f2c21b88b">XUARTPSV_UARTRIS_CTSRMIS</a>&#160;&#160;&#160;0x00000002U</td></tr>
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<tr class="memitem:gabdd920d80d9cc6482c1a3895d73ae53b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gabdd920d80d9cc6482c1a3895d73ae53b">XUARTPSV_UARTRIS_RIRMIS</a>&#160;&#160;&#160;0x00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Masked Interrupt Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTMIS Register is the masked interrupt status register.</p>
<p>It is a read-only register. This register returns the current masked status value of the corresponding interrupt. A write has no effect.</p>
<p>Masked Interrupt Status Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:gadff4af3cfaca4993a30c5c5266ae529e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gadff4af3cfaca4993a30c5c5266ae529e">XUARTPSV_UARTMIS_OEMIS</a>&#160;&#160;&#160;0x00000400U</td></tr>
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<tr class="memitem:gaa11b496c8d914bc125243a4932d49f21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaa11b496c8d914bc125243a4932d49f21">XUARTPSV_UARTMIS_BEMIS</a>&#160;&#160;&#160;0x00000200U</td></tr>
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<tr class="memitem:ga4e2026709077622fc92091da174c5905"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga4e2026709077622fc92091da174c5905">XUARTPSV_UARTMIS_PEMIS</a>&#160;&#160;&#160;0x00000100U</td></tr>
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<tr class="memitem:ga3a251a341d9ecb4813f82e327374ab52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga3a251a341d9ecb4813f82e327374ab52">XUARTPSV_UARTMIS_FEMIS</a>&#160;&#160;&#160;0x00000080U</td></tr>
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<tr class="memitem:ga52ca7c517d0f0c8a6f0fd1d8e8d7eddc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga52ca7c517d0f0c8a6f0fd1d8e8d7eddc">XUARTPSV_UARTMIS_RTMIS</a>&#160;&#160;&#160;0x00000040U</td></tr>
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<tr class="separator:ga52ca7c517d0f0c8a6f0fd1d8e8d7eddc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab28d89546e345e5e3cbf9ce1eb25dfb8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab28d89546e345e5e3cbf9ce1eb25dfb8">XUARTPSV_UARTMIS_TXMIS</a>&#160;&#160;&#160;0x00000020U</td></tr>
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<tr class="memitem:ga9b2d4bf25218bb91c240ec1bc24faaf3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9b2d4bf25218bb91c240ec1bc24faaf3">XUARTPSV_UARTMIS_RXMIS</a>&#160;&#160;&#160;0x00000010U</td></tr>
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<tr class="memitem:gac6d23a13af260f2f0c154b43ab1992af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac6d23a13af260f2f0c154b43ab1992af">XUARTPSV_UARTMIS_DSRMMIS</a>&#160;&#160;&#160;0x00000008U</td></tr>
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<tr class="memitem:ga404b01324241b4d548ee09612c5a2d81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga404b01324241b4d548ee09612c5a2d81">XUARTPSV_UARTMIS_DCDMMIS</a>&#160;&#160;&#160;0x00000004U</td></tr>
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<tr class="memitem:ga33c72fae0f65bb09790bcee04319bd93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga33c72fae0f65bb09790bcee04319bd93">XUARTPSV_UARTMIS_CTSMMIS</a>&#160;&#160;&#160;0x00000002U</td></tr>
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<tr class="memitem:gab2469c1814f75873fb5e60b0de9de83b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab2469c1814f75873fb5e60b0de9de83b">XUARTPSV_UARTMIS_RIRMMIS</a>&#160;&#160;&#160;0x00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Clear Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTICR Register is the interrupt clear register and is write-only.</p>
<p>On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.</p>
<p>Interrupt Clear Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga4c5b60663f12908dd6339c6755867a1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga4c5b60663f12908dd6339c6755867a1e">XUARTPSV_UARTICR_OEIC</a>&#160;&#160;&#160;0x00000400U</td></tr>
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<tr class="memitem:ga4552b07c36b5ae999d719353bbde4f11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga4552b07c36b5ae999d719353bbde4f11">XUARTPSV_UARTICR_BEIC</a>&#160;&#160;&#160;0x00000200U</td></tr>
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<tr class="memitem:ga6afe897d1f04d1abbac48e51edbf40ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6afe897d1f04d1abbac48e51edbf40ba">XUARTPSV_UARTICR_PEIC</a>&#160;&#160;&#160;0x00000100U</td></tr>
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<tr class="memitem:ga220436abcfb954b74153ff42fbc33a7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga220436abcfb954b74153ff42fbc33a7d">XUARTPSV_UARTICR_FEIC</a>&#160;&#160;&#160;0x00000080U</td></tr>
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<tr class="memitem:ga9f7cfbeb49a16ef17c5b8a86cc4e1c4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9f7cfbeb49a16ef17c5b8a86cc4e1c4c">XUARTPSV_UARTICR_RTIC</a>&#160;&#160;&#160;0x00000040U</td></tr>
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<tr class="memitem:ga20a58efada7dba278f69bc89e3420a5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga20a58efada7dba278f69bc89e3420a5d">XUARTPSV_UARTICR_TXIC</a>&#160;&#160;&#160;0x00000020U</td></tr>
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<tr class="memitem:ga0f59c51a960b277b884f500605481760"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga0f59c51a960b277b884f500605481760">XUARTPSV_UARTICR_RXIC</a>&#160;&#160;&#160;0x00000010U</td></tr>
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<tr class="memitem:gac8676778cdc68b2b95a988c84458d121"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac8676778cdc68b2b95a988c84458d121">XUARTPSV_UARTICR_DSRMIC</a>&#160;&#160;&#160;0x00000008U</td></tr>
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<tr class="memitem:ga9a48b79148ce7ab6364636795a100055"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9a48b79148ce7ab6364636795a100055">XUARTPSV_UARTICR_DCDMIC</a>&#160;&#160;&#160;0x00000004U</td></tr>
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<tr class="separator:ga9a48b79148ce7ab6364636795a100055"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9fbdc084c6d530db5cb4cdd2fc03678a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9fbdc084c6d530db5cb4cdd2fc03678a">XUARTPSV_UARTICR_CTSMIC</a>&#160;&#160;&#160;0x00000002U</td></tr>
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<tr class="memitem:ga58dd5fadf63d2dc26cbaf1df95b2653f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga58dd5fadf63d2dc26cbaf1df95b2653f">XUARTPSV_UARTICR_RIMIC</a>&#160;&#160;&#160;0x00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DMA Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTDMACR Register is the DMA control register.</p>
<p>It is a read/write register. All the bits are cleared to 0 on reset.</p>
<p>DMA Control Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:ga9d66e0901ccf58380f2ba158b3cb65a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9d66e0901ccf58380f2ba158b3cb65a3">XUARTPSV_UARTDMACR_DMAONERR</a>&#160;&#160;&#160;0x00000004U</td></tr>
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<tr class="separator:ga9d66e0901ccf58380f2ba158b3cb65a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga57c24eca5b8add1724d156e4d77068bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga57c24eca5b8add1724d156e4d77068bb">XUARTPSV_UARTDMACR_TXDMAE</a>&#160;&#160;&#160;0x00000002U</td></tr>
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<tr class="separator:ga57c24eca5b8add1724d156e4d77068bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7d18d206cd390d5c0f9be21f151b775"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac7d18d206cd390d5c0f9be21f151b775">XUARTPSV_UARTDMACR_RXDMAE</a>&#160;&#160;&#160;0x00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Integer Baud Rate Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTIBRD Register is the integer part of the baud rate divisor value </p>
</div></td></tr>
<tr class="memitem:gab1611615b33b1f7a1010d0e571473b0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab1611615b33b1f7a1010d0e571473b0d">XUARTPSV_UARTIBRD_BAUD_DIVINT_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gab1611615b33b1f7a1010d0e571473b0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 UARTIBRD bit mask  <a href="group__uartpsv.html#gab1611615b33b1f7a1010d0e571473b0d">More...</a><br/></td></tr>
<tr class="separator:gab1611615b33b1f7a1010d0e571473b0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab18e6fd8e864a6ff05bacb9edcf80ca9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab18e6fd8e864a6ff05bacb9edcf80ca9">XUARTPSV_UARTIBRD_BAUD_DIVINT_RESET_VAL</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gab18e6fd8e864a6ff05bacb9edcf80ca9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartpsv.html#gab18e6fd8e864a6ff05bacb9edcf80ca9">More...</a><br/></td></tr>
<tr class="separator:gab18e6fd8e864a6ff05bacb9edcf80ca9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Fractional Baud Rate Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The UARTFBRD Register is the fractional part of the baud rate divisor value</p>
<p>Baud rate divisor BAUDDIV = (FUARTCLK/(16xBaud rate)) where FUARTCLK is the UART reference clock frequency The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC) </p>
</div></td></tr>
<tr class="memitem:ga633d2f574860bd31ec76274313b9bcec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga633d2f574860bd31ec76274313b9bcec">XUARTPSV_UARTFBRD_BAUD_DIVFRAC_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:ga633d2f574860bd31ec76274313b9bcec"><td class="mdescLeft">&#160;</td><td class="mdescRight">6 UARTFBRD bit mask  <a href="group__uartpsv.html#ga633d2f574860bd31ec76274313b9bcec">More...</a><br/></td></tr>
<tr class="separator:ga633d2f574860bd31ec76274313b9bcec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga339185fe91d271fd13697df0d298ac91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga339185fe91d271fd13697df0d298ac91">XUARTPSV_UARTFBRD_BAUD_DIVFRAC_RESET_VAL</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga339185fe91d271fd13697df0d298ac91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartpsv.html#ga339185fe91d271fd13697df0d298ac91">More...</a><br/></td></tr>
<tr class="separator:ga339185fe91d271fd13697df0d298ac91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver Timeout Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the receiver timeout register (RTR) to detect an idle condition on the receiver data line. </p>
</div></td></tr>
<tr class="memitem:ga173730ca6773ddb922dab7bdcb87a631"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga173730ca6773ddb922dab7bdcb87a631">XUARTPSV_RXTOUT_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga173730ca6773ddb922dab7bdcb87a631"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable time out.  <a href="group__uartpsv.html#ga173730ca6773ddb922dab7bdcb87a631">More...</a><br/></td></tr>
<tr class="separator:ga173730ca6773ddb922dab7bdcb87a631"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d0d43149b394b78fda02b2c1be1e77b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga5d0d43149b394b78fda02b2c1be1e77b">XUARTPSV_RXTOUT_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga5d0d43149b394b78fda02b2c1be1e77b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartpsv.html#ga5d0d43149b394b78fda02b2c1be1e77b">More...</a><br/></td></tr>
<tr class="separator:ga5d0d43149b394b78fda02b2c1be1e77b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver FIFO Trigger Level Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at which the RX FIFO triggers an interrupt event. </p>
</div></td></tr>
<tr class="memitem:gab1fbd61669bd25682679f75ff287e930"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab1fbd61669bd25682679f75ff287e930">XUARTPSV_RXWM_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gab1fbd61669bd25682679f75ff287e930"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable RX trigger interrupt.  <a href="group__uartpsv.html#gab1fbd61669bd25682679f75ff287e930">More...</a><br/></td></tr>
<tr class="separator:gab1fbd61669bd25682679f75ff287e930"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafbbddd771bc593e516b514a95efc26b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaafbbddd771bc593e516b514a95efc26b">XUARTPSV_RXWM_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:gaafbbddd771bc593e516b514a95efc26b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartpsv.html#gaafbbddd771bc593e516b514a95efc26b">More...</a><br/></td></tr>
<tr class="separator:gaafbbddd771bc593e516b514a95efc26b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1dea1ef860544589c3e67c5cf2227c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1dea1ef860544589c3e67c5cf2227c97">XUARTPSV_RXWM_RESET_VAL</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga1dea1ef860544589c3e67c5cf2227c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartpsv.html#ga1dea1ef860544589c3e67c5cf2227c97">More...</a><br/></td></tr>
<tr class="separator:ga1dea1ef860544589c3e67c5cf2227c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Transmit FIFO Trigger Level Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at which the TX FIFO triggers an interrupt event. </p>
</div></td></tr>
<tr class="memitem:gaddc69b17fa1e368e5aaecb7944607732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaddc69b17fa1e368e5aaecb7944607732">XUARTPSV_TXWM_MASK</a>&#160;&#160;&#160;0x0000003FU</td></tr>
<tr class="memdesc:gaddc69b17fa1e368e5aaecb7944607732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bits mask.  <a href="group__uartpsv.html#gaddc69b17fa1e368e5aaecb7944607732">More...</a><br/></td></tr>
<tr class="separator:gaddc69b17fa1e368e5aaecb7944607732"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6df4cb99023a731978bd2bc1cf17ed3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gad6df4cb99023a731978bd2bc1cf17ed3">XUARTPSV_TXWM_RESET_VAL</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gad6df4cb99023a731978bd2bc1cf17ed3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value.  <a href="group__uartpsv.html#gad6df4cb99023a731978bd2bc1cf17ed3">More...</a><br/></td></tr>
<tr class="separator:gad6df4cb99023a731978bd2bc1cf17ed3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Modem Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register (MODEMCR) controls the interface with the modem or data set, or a peripheral device emulating a modem. </p>
</div></td></tr>
<tr class="memitem:gac0788c413637618883eb2da800a4af28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac0788c413637618883eb2da800a4af28">XUARTPSV_MODEMCR_FCM</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gac0788c413637618883eb2da800a4af28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow control mode.  <a href="group__uartpsv.html#gac0788c413637618883eb2da800a4af28">More...</a><br/></td></tr>
<tr class="separator:gac0788c413637618883eb2da800a4af28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9454c4327718d5ad2d7f2e21f7a23d5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9454c4327718d5ad2d7f2e21f7a23d5d">XUARTPSV_MODEMCR_RTS</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga9454c4327718d5ad2d7f2e21f7a23d5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Request to send.  <a href="group__uartpsv.html#ga9454c4327718d5ad2d7f2e21f7a23d5d">More...</a><br/></td></tr>
<tr class="separator:ga9454c4327718d5ad2d7f2e21f7a23d5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6213c92e85547c4cac6483b95c428cc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6213c92e85547c4cac6483b95c428cc9">XUARTPSV_MODEMCR_DTR</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga6213c92e85547c4cac6483b95c428cc9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data terminal ready.  <a href="group__uartpsv.html#ga6213c92e85547c4cac6483b95c428cc9">More...</a><br/></td></tr>
<tr class="separator:ga6213c92e85547c4cac6483b95c428cc9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Modem Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register (MODEMSR) indicates the current state of the control lines from a modem, or another peripheral device, to the CPU.</p>
<p>In addition, four bits of the modem status register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state.</p>
<p>Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem status interrupt is generated and this is reflected in the modem status register. </p>
</div></td></tr>
<tr class="memitem:gaad951ca80e214eeb794c593290a9aa25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaad951ca80e214eeb794c593290a9aa25">XUARTPSV_MODEMSR_FCMS</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:gaad951ca80e214eeb794c593290a9aa25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flow control mode (FCMS)  <a href="group__uartpsv.html#gaad951ca80e214eeb794c593290a9aa25">More...</a><br/></td></tr>
<tr class="separator:gaad951ca80e214eeb794c593290a9aa25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc4af961f5145f1b0fca9d432b02f03a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gacc4af961f5145f1b0fca9d432b02f03a">XUARTPSV_MODEMSR_DCD</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gacc4af961f5145f1b0fca9d432b02f03a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of DCD input.  <a href="group__uartpsv.html#gacc4af961f5145f1b0fca9d432b02f03a">More...</a><br/></td></tr>
<tr class="separator:gacc4af961f5145f1b0fca9d432b02f03a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1608b91aa0312b03d6db57cbb0c5903d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga1608b91aa0312b03d6db57cbb0c5903d">XUARTPSV_MODEMSR_RI</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga1608b91aa0312b03d6db57cbb0c5903d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of RI input.  <a href="group__uartpsv.html#ga1608b91aa0312b03d6db57cbb0c5903d">More...</a><br/></td></tr>
<tr class="separator:ga1608b91aa0312b03d6db57cbb0c5903d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6acb0a5e2f20ca78b883f020a203b7ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6acb0a5e2f20ca78b883f020a203b7ca">XUARTPSV_MODEMSR_DSR</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga6acb0a5e2f20ca78b883f020a203b7ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of DSR input.  <a href="group__uartpsv.html#ga6acb0a5e2f20ca78b883f020a203b7ca">More...</a><br/></td></tr>
<tr class="separator:ga6acb0a5e2f20ca78b883f020a203b7ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6514479e328267f2d6e9cf7b387d3693"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6514479e328267f2d6e9cf7b387d3693">XUARTPSV_MODEMSR_CTS</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga6514479e328267f2d6e9cf7b387d3693"><td class="mdescLeft">&#160;</td><td class="mdescRight">Complement of CTS input.  <a href="group__uartpsv.html#ga6514479e328267f2d6e9cf7b387d3693">More...</a><br/></td></tr>
<tr class="separator:ga6514479e328267f2d6e9cf7b387d3693"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14b093e218c770247b4679be965c9c04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga14b093e218c770247b4679be965c9c04">XUARTPSV_MODEMSR_DDCD</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga14b093e218c770247b4679be965c9c04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delta DCD indicator.  <a href="group__uartpsv.html#ga14b093e218c770247b4679be965c9c04">More...</a><br/></td></tr>
<tr class="separator:ga14b093e218c770247b4679be965c9c04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8e83610d3828dadeed6432ec89ffb20"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gae8e83610d3828dadeed6432ec89ffb20">XUARTPSV_MODEMSR_TERI</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gae8e83610d3828dadeed6432ec89ffb20"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trailing Edge Ring Indicator.  <a href="group__uartpsv.html#gae8e83610d3828dadeed6432ec89ffb20">More...</a><br/></td></tr>
<tr class="separator:gae8e83610d3828dadeed6432ec89ffb20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab87fd2e43991665d8975bd95d9e8707e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gab87fd2e43991665d8975bd95d9e8707e">XUARTPSV_MODEMSR_DDSR</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gab87fd2e43991665d8975bd95d9e8707e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change of DSR.  <a href="group__uartpsv.html#gab87fd2e43991665d8975bd95d9e8707e">More...</a><br/></td></tr>
<tr class="separator:gab87fd2e43991665d8975bd95d9e8707e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ee1bfca92eeb17e0279b34fc6cc17a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga0ee1bfca92eeb17e0279b34fc6cc17a2">XUARTPSV_MODEMSR_DCTS</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga0ee1bfca92eeb17e0279b34fc6cc17a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change of CTS.  <a href="group__uartpsv.html#ga0ee1bfca92eeb17e0279b34fc6cc17a2">More...</a><br/></td></tr>
<tr class="separator:ga0ee1bfca92eeb17e0279b34fc6cc17a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Flow Delay Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Operation of the flow delay register (FLOWDEL) is very similar to the receive FIFO trigger register.</p>
<p>An internal trigger signal activates when the FIFO is filled to the level set by this register. This trigger will not cause an interrupt, although it can be read through the channel status register. In hardware flow control mode, RTS is deactivated when the trigger becomes active. RTS only resets when the FIFO level is four less than the level of the flow delay trigger and the flow delay trigger is not activated. A value less than 4 disables the flow delay. </p>
</div></td></tr>
<tr class="memitem:ga5f215e3b57a0c0cf69b85241fcd4d226"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga5f215e3b57a0c0cf69b85241fcd4d226">XUARTPSV_FLOWDEL_MASK</a>&#160;&#160;&#160;<a class="el" href="group__uartpsv.html#gaafbbddd771bc593e516b514a95efc26b">XUARTPSV_RXWM_MASK</a></td></tr>
<tr class="memdesc:ga5f215e3b57a0c0cf69b85241fcd4d226"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid bit mask.  <a href="group__uartpsv.html#ga5f215e3b57a0c0cf69b85241fcd4d226">More...</a><br/></td></tr>
<tr class="separator:ga5f215e3b57a0c0cf69b85241fcd4d226"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Receiver FIFO Byte Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The Receiver FIFO Status register is used to have a continuous monitoring of the raw unmasked byte status information.</p>
<p>The register contains frame, parity and break status information for the top four bytes in the RX FIFO.</p>
<p>Receiver FIFO Byte Status Register Bit Definition </p>
</div></td></tr>
<tr class="memitem:gac07640e5208fd4b2bbf9a7df50e49987"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac07640e5208fd4b2bbf9a7df50e49987">XUARTPSV_RXBS_BYTE3_BRKE</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:gac07640e5208fd4b2bbf9a7df50e49987"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Break Error.  <a href="group__uartpsv.html#gac07640e5208fd4b2bbf9a7df50e49987">More...</a><br/></td></tr>
<tr class="separator:gac07640e5208fd4b2bbf9a7df50e49987"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8834be04fdcb72d04079952740db5bdb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga8834be04fdcb72d04079952740db5bdb">XUARTPSV_RXBS_BYTE3_FRME</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga8834be04fdcb72d04079952740db5bdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Frame Error.  <a href="group__uartpsv.html#ga8834be04fdcb72d04079952740db5bdb">More...</a><br/></td></tr>
<tr class="separator:ga8834be04fdcb72d04079952740db5bdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f28311ee75c74096b64e30ab7448c04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga7f28311ee75c74096b64e30ab7448c04">XUARTPSV_RXBS_BYTE3_PARE</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga7f28311ee75c74096b64e30ab7448c04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte3 Parity Error.  <a href="group__uartpsv.html#ga7f28311ee75c74096b64e30ab7448c04">More...</a><br/></td></tr>
<tr class="separator:ga7f28311ee75c74096b64e30ab7448c04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5faa10d529dbfdab41da0e9d4cc938c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gad5faa10d529dbfdab41da0e9d4cc938c">XUARTPSV_RXBS_BYTE2_BRKE</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:gad5faa10d529dbfdab41da0e9d4cc938c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Break Error.  <a href="group__uartpsv.html#gad5faa10d529dbfdab41da0e9d4cc938c">More...</a><br/></td></tr>
<tr class="separator:gad5faa10d529dbfdab41da0e9d4cc938c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d0546e6fab0ef8ba0977833231a6d91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga4d0546e6fab0ef8ba0977833231a6d91">XUARTPSV_RXBS_BYTE2_FRME</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga4d0546e6fab0ef8ba0977833231a6d91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Frame Error.  <a href="group__uartpsv.html#ga4d0546e6fab0ef8ba0977833231a6d91">More...</a><br/></td></tr>
<tr class="separator:ga4d0546e6fab0ef8ba0977833231a6d91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa29b978453f802c0ada625787b7de014"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gaa29b978453f802c0ada625787b7de014">XUARTPSV_RXBS_BYTE2_PARE</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gaa29b978453f802c0ada625787b7de014"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte2 Parity Error.  <a href="group__uartpsv.html#gaa29b978453f802c0ada625787b7de014">More...</a><br/></td></tr>
<tr class="separator:gaa29b978453f802c0ada625787b7de014"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a36e47e59e3984215c8059ed6908f69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga8a36e47e59e3984215c8059ed6908f69">XUARTPSV_RXBS_BYTE1_BRKE</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga8a36e47e59e3984215c8059ed6908f69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Break Error.  <a href="group__uartpsv.html#ga8a36e47e59e3984215c8059ed6908f69">More...</a><br/></td></tr>
<tr class="separator:ga8a36e47e59e3984215c8059ed6908f69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga344cd4473a0985c163d3e45fab243e76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga344cd4473a0985c163d3e45fab243e76">XUARTPSV_RXBS_BYTE1_FRME</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga344cd4473a0985c163d3e45fab243e76"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Frame Error.  <a href="group__uartpsv.html#ga344cd4473a0985c163d3e45fab243e76">More...</a><br/></td></tr>
<tr class="separator:ga344cd4473a0985c163d3e45fab243e76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9db1d46c3385b585cb3af128a6df3a23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga9db1d46c3385b585cb3af128a6df3a23">XUARTPSV_RXBS_BYTE1_PARE</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga9db1d46c3385b585cb3af128a6df3a23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte1 Parity Error.  <a href="group__uartpsv.html#ga9db1d46c3385b585cb3af128a6df3a23">More...</a><br/></td></tr>
<tr class="separator:ga9db1d46c3385b585cb3af128a6df3a23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac45207fa78a8cd222a9db94bb7cea144"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gac45207fa78a8cd222a9db94bb7cea144">XUARTPSV_RXBS_BYTE0_BRKE</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gac45207fa78a8cd222a9db94bb7cea144"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Break Error.  <a href="group__uartpsv.html#gac45207fa78a8cd222a9db94bb7cea144">More...</a><br/></td></tr>
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<tr class="memitem:ga99af1e795dcd2a309121ab431402e8e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga99af1e795dcd2a309121ab431402e8e5">XUARTPSV_RXBS_BYTE0_FRME</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga99af1e795dcd2a309121ab431402e8e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Frame Error.  <a href="group__uartpsv.html#ga99af1e795dcd2a309121ab431402e8e5">More...</a><br/></td></tr>
<tr class="separator:ga99af1e795dcd2a309121ab431402e8e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd3e849759fc39c8dd3cbd14252d547b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#gafd3e849759fc39c8dd3cbd14252d547b">XUARTPSV_RXBS_BYTE0_PARE</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gafd3e849759fc39c8dd3cbd14252d547b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte0 Parity Error.  <a href="group__uartpsv.html#gafd3e849759fc39c8dd3cbd14252d547b">More...</a><br/></td></tr>
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<tr class="memitem:ga5591fe90f5f7e0d1c44ad924c5579d46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga5591fe90f5f7e0d1c44ad924c5579d46">XUARTPSV_RXBS_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga5591fe90f5f7e0d1c44ad924c5579d46"><td class="mdescLeft">&#160;</td><td class="mdescRight">3 bit RX byte status mask  <a href="group__uartpsv.html#ga5591fe90f5f7e0d1c44ad924c5579d46">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga24308126daae7b67de1790b345933598"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga24308126daae7b67de1790b345933598">XUartPsv_SendByte</a> (UINTPTR BaseAddress, u8 Data)</td></tr>
<tr class="memdesc:ga24308126daae7b67de1790b345933598"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends one byte using the device.  <a href="group__uartpsv.html#ga24308126daae7b67de1790b345933598">More...</a><br/></td></tr>
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<tr class="memitem:ga6d764b77ee5e8f535ce523a9df1f2ddc"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga6d764b77ee5e8f535ce523a9df1f2ddc">XUartPsv_RecvByte</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga6d764b77ee5e8f535ce523a9df1f2ddc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives a byte from the device.  <a href="group__uartpsv.html#ga6d764b77ee5e8f535ce523a9df1f2ddc">More...</a><br/></td></tr>
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<tr class="memitem:ga99e7a45fe3e00b94d58f540acf6328af"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartpsv.html#ga99e7a45fe3e00b94d58f540acf6328af">XUartPsv_ResetHw</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga99e7a45fe3e00b94d58f540acf6328af"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets UART.  <a href="group__uartpsv.html#ga99e7a45fe3e00b94d58f540acf6328af">More...</a><br/></td></tr>
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